Quasi-delay-insensitive circuit
http://dbpedia.org/resource/Quasi-delay-insensitive_circuit
In digital logic design, an asynchronous circuit is quasi delay-insensitive (QDI) when it operates correctly, independent of gate and wire delay with the weakest exception necessary to be turing-complete.
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Quasi-delay-insensitive circuit
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2817767
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1120549254
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December 2021
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timing
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verification
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layout
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chips
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sizing
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synthesis
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that the article uses very unusual style of citation: it excessively relies on the html-tag attribute . It would probably be better to use a numeric style. Please discuss.
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In digital logic design, an asynchronous circuit is quasi delay-insensitive (QDI) when it operates correctly, independent of gate and wire delay with the weakest exception necessary to be turing-complete.
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34764
